1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection circuitry, and in particular to ESD protection clamp circuitry for circuits operating at low power supply voltages.
2. Description of the Related Art
Electrostatic discharge (ESD) in semiconductor integrated circuits is a well known problem. The presence of a sudden and undesired voltage spike within or at the interface pin of an integrated circuit can cause physical destruction of one or more portions of the circuitry. This is particularly true for field effect transistors, such as metal oxide semiconductor (MOS) devices, where the thin gate oxide is easily destroyed by large voltage spikes. Similarly, the PN junctions of bipolar devices can also be degraded if not destroyed.
This problem becomes increasingly acute, particularly for circuits employing both complementary MOS and bipolar processes, as the power supply voltages and signal levels decrease, e.g., 3.3 volts, 2.5 volts, 1.8 volts, and so on. As these types of circuits have developed, it has become increasingly common to provide ESD protection through the use of active clamp circuitry, many types of which are well known in the art.
Referring to FIG. 1, one conventional form of ESD clamp circuitry 10a has the clamp circuitry coupled between the signal node, e.g., defined as the interconnection between an input/output pad P1 and further internal circuitry 12, and the circuit reference terminal, e.g., ground. A serially coupled diode D1 and resistor R1 serve as control circuitry for a bipolar transistor Q1 which serves as the ESD current shunting device. As the ESD voltage increases and becomes sufficiently large to cause breakdown within the diode D1, a control current Icon flows through the diode D1 and resistor R1. This produces a voltage VI across the resistor R1 and a base current I1 for the transistor Q1. This causes the transistor Q1 to turn on and conduct current Iesd associated with the ESD pulse to the circuit reference node, or ground.
Referring to FIG. 2, a similar circuit 10b uses a capacitor C1 instead of a diode D1. The rapid rise of the ESD voltage causes a current to flow briefly through the capacitor C1. This, in turn, causes the voltage VI to appear across the resistor and turn on the current shunting transistor, in this example an N-channel MOS transistor N1, thereby causing the ESD current Iesd to be shunted to the circuit reference node.
While these circuits 10a, 10b, and others similar to these (e.g., where the control devices in the form of diodes and capacitors may be mixed and matched with different types of current shunting devices in the form of bipolar transistors or MOS transistors) have performed reasonably well up to now, such circuits do not perform as well with the lower power supply voltages and signal levels which have become more prevalent. At reduced power supply voltages and signal levels, leakage currents become more of a problem as the leakage currents become proportionately higher with respect to the power supply voltages and signal levels, and such leakage currents become more likely to be amplified by the clamp, thereby causing false triggering.